The present invention relates to a nonvolatile semiconductor memory capable of data writing and of retaining substantially permanently the data once written.
A nonvolatile semiconductor memory, particularly an EPROM (Erasable Programmable Read Only Memory) having a floating gate, is simple as regards the structure of its memory cells and thus is suitable for large-scale integration. At present, EPROMs of large capacities such as 256 Kbit, 512 Kbit, and 1 Mbit have been developed and put to practical use. In accordance with progress in computer systems using such EPROMs, the EPROM is required to operate at a high speed, thus resulting in serious demand for EPROMs of high reliability.
Attempts to improve the operating speed of EPROMs are reported by S. Moietal. in, for example, "1984 Symposium on VLSI Technology, Digest of Technical Papers", pages 40 and 41. It is reported that a titanium silicide layer, is formed on the surface of a polysilicon layer, in an attempt to decrease the resistance of the word line. It is also reported that the word line is formed of a polysilicon layer and a molybdenum silicide layer laminated thereon, i.e., a so-called "polycide structure", again in an attempt to decrease the resistance of the word line.
In the memory cells of these basic EPROMs, however, the electrons stored in the floating gate, which is electrically insulated from other members, should be retained over a long period of time without being released during operation of the EPROMs.
FIGS. 1A and 1B collectively show the memory cell array portion of an EPROM in which the word line is of the polycide structure, in order to decrease the resistance of the word line, in which FIG. 1A is a plan view showing the pattern of the memory cell array and FIG. 1B is a cross-sectional view along line A--A of FIG. 1A. As can be seen from the drawings, the EPROM comprises p-type silicon semiconductor substrate 31, field insulation film 32 selectively formed on the surface of the substrate 31, source region 33 consisting of an n-type diffusion region, drain region 34 which also consists of an n-type diffusion region, channel region 35 positioned between source region 33 and drain region 34, gate insulation film 36 formed on channel region 35, floating gate 37 of a memory cell formed of a first polysilicon layer, gate insulation film 38 formed to cover floating gate 37, and word line 39 formed of a second polysilicon layer. Word line 39 also acts as a control gate of the memory cell. The EPROM further comprises molybdenum silicide layer 40 formed directly on word line 39 to decrease the resistance of the word line, bit line 41 formed of a metal, e.g., aluminum, and contact hole 42 serving to connect drain region 34 of each memory cell to each bit line 41.
In the EPROM of this particular construction, the charge-retaining property of floating gate 37 depends on the insulating property of gate insulation films 36 and 38, which are generally formed of silicon oxide. It follows that in the case of using a silicon oxide film through which leak current tends to flow easily, i.e., which is low in barrier height, it is impossible to ensure a sufficiently high charge-retaining property, leading to a low reliability in terms of the ability of the EPROM to retain stored data.
In the conventional method of forming a titanium silicide layer on the surface of a polysilicon layer, the step of forming a silicon oxide layer covering the gate insulation film is completed before the titanium silicide layer is formed thereon, thus making it possible to obtain a floating gate covered with a high quality silicon oxide film. However, titanium is highly reactive with silicon oxide, and thus, the titanium contained in the titanium silicide layer reacts vigorously with the silicon oxide film formed in advance. In addition, the titanium atoms are downwardly diffused toward the inner region of the substrate, along the grain boundry of the polysilicon, so as to markedly deteriorate the insulating property of the silicon oxide film.
FIG. 1B shows that the substantial word line is of two-layer structure, consisting of second polysilicon layer 39 and molybdenum silicide layer 40. The general method of obtaining this particular construction comprises the first step of depositing gate insulation film 38 on floating gate 37, followed by depositing, in succession, second polysilicon layer 39 and molybdenum silicide layer 40. Then, uppermost silicide layer 40 is precisely patterned by photolithography, followed by etching, in succession, molybdenum silicide layer 40, second polysilicon layer 39, gate insulating film 38, and floating gate 37, by means of a self-aligned etching technique. After the etching, source region 33 and drain region 34 are formed by diffusion, followed by oxidizing the surface regions of molybdenum silicide layer 40, second polysilicon layer 39, and floating gate 37, so as to form a silicon oxide film. It follows that the silicon oxide film positioned on the surface of floating gate 37 is caused to contain traces of molybdeum, leading to deterioration in its electrical insulating properties. In other words, electric current tends to leak through floating gate 37. It should also be noted that molybdenum silicide layer 40 crosses many sharply-stepped portions X at the edges of floating gates 37, as is shown in FIG. 1B. As a result, deep notches are formed in molybdenum silicide layer 40, resulting in it having a high electrical resistance.
In order to improve the access speed of an EPROM, it is necessary to suppress the electrical resistance of the word line as much as possible. A polycide structure has been proposed for lowering the resistance of the word line, which uses tungsten, titanium, molybdenum, etc. Such a structure, however, gives rise to sharply stepped portions X, as is shown in FIG. 1B, when it is applied to an EPROM, resulting in a failure to lower the resistance of the word line, as desired. In short, the prior art as shown in FIGS. 1A and 1B is incapable of improving the access speed of an EPROM. (First disadvantage of the prior art).
Providing a two-aluminum-layer structure in which a second aluminum layer is formed on the contact region between a first aluminum layer and a diffusion layer is an effective method of lowering the resistance of the word line. In this case, however, the second aluminum layer tends to break above the contact region. Thus, in order to lower the resistance of word line 39, without using silicide layer 40 in the conventional cell structure shown in FIG. 1A, it is necessary to provide second aluminum layer 400, as is denoted by a broken line in FIG. 1A, in place of silicide layer 40 shown in FIG. 1B. Of course, a signal, being same as the signal conducted through word line 39, is conducted through second aluminum layer 400. In this case, however, sharply stepped portions X are formed in second aluminum layer 400. To suppress the increase in resistance caused by the stepped portions, it is necessary to make second aluminum layer 400 wider than first aluminum layer 41. Naturally, second aluminum layer 400 is rendered wider than polysilicon layer 39 of the cell, as can be seen from FIG. 1A. It follows that the transmitting of an ultraviolet light to reach floating gate (first polysilicon layer) 37 is obstructed, resulting in a longer time required for data erasure. (Second disadvantage of the prior art)